Field of the Invention
The disclosure relates generally to ESD protection circuits, and more particularly it relates to ESD protection circuits with non-snapback devices and snapback devices that are cascaded.
Description of the Related Art
The integrated circuits can be seriously damaged by any kind of electrostatic discharge event. The main electrostatic discharge mechanism comes from the human body, which is called Human Body Model (HBM). Several amperes of peak current is generated by the human body in about 100 nanoseconds and flows to an integrated circuit, which leads to damage of the integrated circuit. The second electrostatic discharge mechanism comes from a metal object, which is called Machine Model (MM). The current generated by the Machine Model has a shorter rise time and a higher current level than that by the Human Body Model. The third mechanism is the Charged-Device Model (CDM), in which the accumulated charge in the integrated circuit is discharged to the ground in less than 0.5 nanoseconds of rise time.
However, the holding voltage of the ESD protection circuit is usually unable to be higher than the operation voltage of the integrated circuit (i.e., the supply voltage of the integrated circuit) in the high-voltage and BCD manufacturing process. It causes the ESD protection circuit to experience latchup or a latchup-like effect due to interference while the integrated circuit is working, which leads to the ESD protection circuit becoming damaged. In addition, the trigger voltage of the ESD protection circuit is often raised for the higher holding voltage, such that the ESD protection circuit is not able to perfectly protect the integrated circuit. Therefore, we need to more effectively control the holding voltage and the trigger voltage of the ESD protection circuit.